Modern computing devices utilize a variety of kinds of memory devices to store and access information. Memory devices include the general classes of random access memories (RAM) and read only memories (ROM). These classes further contain static RAM (SRAM), dynamic RAM (DRAM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable PROM (EEPROM), as well as FLASH memory, and the like. Most memory devices employ an internal architecture in the form of an array memory of bit cells, containing plural rows and plural intersecting columns.
A memory cell is placed at each intersecting row and column in the array. Typically, a particular memory cell is accessed by activating its row and then reading or writing the state of its column. Memory sizes are defined by the row and column architecture. For example, a 1024 row by 1024 column memory array defines a memory device having one megabit of memory cells. The array rows are referred to as wordlines and the array columns are referred to as bitlines.
The trend in semiconductor memory devices has been toward higher circuit density with higher numbers of bit cells per device, lower operating voltages, and higher access speeds. To achieve these high densities there have been, and continue to be, efforts toward scaling down device dimensions (e.g., at sub-micron levels). However, as scaling down device dimensions, bitline-to-bitline leakage may undesirably increase. Further, bitline contact misalignment may increase leakage current between the bitline and substrate silicon areas adjacent to the bitlines. To prevent bitline contact misalignment induced bitline-to-substrate leakage by ensuring that the bitline contact is formed over the bitline, an additional dopant implant can be utilized to increase the size of the bitline diffusion region after the contact has been etched. However, the increased bitline diffusion region may increase bitline-to-bitline leakage by decreasing the distance between bitlines. Thus, the requirement of small features with close spacing between adjacent features requires sophisticated manufacturing techniques.